Method of fabricating flash memory cell

ABSTRACT

A method of fabricating a flash memory cell includes the steps of ion-implanting impurity into a substrate to form a buried region having a striped shape extending in a first direction (Y), depositing an insulating layer on the substrate and selectively etching the insulating layer to form a field insulating layer and a plurality of contact holes that expose the substrate in a matrix form. The method further includes forming a gate insulating layer on the exposed substrate in the contact holes, forming self-aligned floating gate on the gate insulating layer in the contact holes, forming an interlevel insulating layer on the floating gate, and forming a plurality of control gates having a striped shape extending in a second direction (X) that crosses the first direction on the interlevel insulating layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a memory cell,and more particularly, to a method of fabricating a flash memory cell.

2. Background of the Related Art

A flash memory cell, which has a laminated structure of a floating gateand a control gate, is a nonvolatile memory device. The flash memorycell is programmed when hot electrons are injected into the floatinggate, and is erased when the electrons of the floating gate are tunneledto a source region or a substrate with a Fowler-Nordheim mechanism. Theflash memory cell has a high erase rate because the memory array cellscan be concurrently erased.

FIG. 1 is a layout of the flash memory cell of the related art. Theflash memory cell includes a buried region 13, a field insulating layer15, a floating gate 19 and a control gate 23. The buried region 13,which is used as data lines, is formed in a stripe shape in a firstdirection, and the field insulating layer 15 for defining an activeregion of the device is formed in a stripe shape in a second direction,which crosses the first direction. The control gate 23 is formed in thesecond direction on the active region between the field insulatinglayers 15. The floating gate 19 is overlapped with the control gate 23.Furthermore, the edged portions on both sides of the floating gate 19overlap with the buried region 13 adjacent thereto.

FIGS. 2A-2D are flow diagrams illustrating the process for fabricating aflash memory cell in accordance with the related art, which showsectional views taken along the line II-II' of FIG. 1.

Referring to FIG. 2A, a mask layer 12 is formed by depositing a siliconoxide or a silicon nitride on a P-type substrate 11 using chemical vapordeposition (CVD). The mask layer 12 is patterned with photolithographyto expose the substrate 11 in a stripe shape in the first direction.Then, an N-type impurity such as phosphorus (P) or arsenic (As) ision-implanted into the exposed portion of the substrate 11 to form theburied region 13.

Referring to FIG. 2B, the mask layer 12 is removed. Then, the fieldinsulating region 15 for defining an active region of device is formedon the field region of the substrate 11 using Local Oxidation of Silicon(LOCOS), and it is formed in a stripe shape in the second directioncrossing the buried region 13.

As shown in FIG. 2C, a thermal oxidation is performed on the exposedportion of the substrate 11 to form the gate oxide layer 17. After apolysilicon doped with impurity is deposited on the field insulatinglayer 15 and the gate oxide layer 17 with CVD, the deposited polysiliconis patterned in a stripe shape in the first direction withphotolithography to form the floating gate 19. The edge on both sides ofthe floating gate 19 overlaps the buried region 13 adjacent to theactive region.

As illustrated in FIG. 2D, an interlevel insulating layer 21 is formedby carrying out an oxidation on the surface of the floating gate 19.Then, a polysilicon doped with impurity and a silicon oxide aresequentially deposited on the field and interlevel insulating layers 15and 21 with CVD. The polysilicon and the silicon oxide are patternedwith photolithography so as to remain in a stripe shape in the seconddirection only in the active region of device, and thus, the controlgate 23 and a cap oxide layer 25 are formed. In the meantime, theportion formed on the field insulating layer 15 of the by floating gate19 is removed.

The flash memory cell as fabricated in the above method, is programmedwhen, with a buried region 13, used as a source, coupled to ground, avoltage Vg applied to the control gate 23 is higher than the voltage Vd(i.e., Vg>Vd) applied to another buried region 13 used as a drainregion. Thus, hot electrons generated in the channel are injected intothe floating gate 19. To erase programmed data in the flash memory cell,the voltage Vs is applied to the buried region used as the source withthe control gate 23 grounded, or with negative voltage applied. Thus,the electrons in the floating gate 19 are tunneled to the buried region13 used as the source region, or the substrate 11.

However, the above-described flash memory cell of the related art methodhas various disadvantages because the fabrication method is too complexin that the field insulating layer and the floating gate are formedthrough separate steps. Further, the floating gate is formed with twoetching steps. Moreover, it is difficult to enhance the integration of adevice using such flash memory cells because of the required space toalign the floating gate with the field insulating layer during the stepof forming the floating gate.

The above references are incorporated by reference herein whereappropriate for appropriate teachings of additional or alternativedetails, features and/or technical background.

SUMMARY OF THE INVENTION

An object of the present invention is to substantially obviate one ormore of the problems caused by limitations and disadvantages of therelated art.

Another object of the present invention is to provide a method offabricating a flash memory cell having a reduced number of processes.

Another object of the present invention is to provide a method offabricating a flash memory cell to enhance the integration of the deviceby the self-alignment of the floating gate with the field insulatinglayer.

To achieve at least these and other objects and advantages in whole orin part and in accordance with the purpose of the present invention, asembodied and broadly described, a method of fabricating a flash memorycell, includes the steps of ion-implanting impurity into a substrate soas to form a buried region having a striped shape in a first direction,depositing an insulating layer on the substrate and selectively etching,the insulating layer to form a field insulating layer and a contacthole, the substrate exposed in a matrix form by the contact hole,forming a gate insulating layer on the exposed substrate, forming afloating gate on the gate insulating layer, forming an interlevelinsulating layer on the floating gate, and forming a control gate havinga striped shape in a second direction that crosses with the firstdirection on a field oxide layer and the interlevel insulating layer.

Additional advantages, objects, and features of the invention will beset forth in part in the description which follows and in part willbecome apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objects and advantages of the invention may be realizedand attained as particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

FIG. 1 is a diagram showing a layout of a related art flash memory cell;

FIGS. 2A-2D are diagrams illustrating a fabricating method for the flashmemory cell of FIG. 1;

FIG. 3 is a diagram illustrating a layout of preferred embodiment of aflash memory cell according to the present invention; and

FIGS. 4A-D are diagrams illustrating a fabricating method for the flashmemory cell of FIG. 3.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 3 shows a layout of a first preferred embodiment of a flash memorycell according to the present invention. The flash memory cell includesa buried region 35, a field insulating layer 37, a contact hole 39, afloating gate 43 and a control gate 47. The buried region 35, which isused as a data line, is formed in a stripe shape in a first direction,and the control gate 47 is formed in a stripe shape in a seconddirection, which crosses the first direction. Preferably the firstdirection is substantially perpendicular to the second direction. Thefield insulating layer 37 defining the active region of a device isformed in a portion other than the contact hole 39, which is formedbetween the buried regions 35 under the control gate 47. The floatinggate 43 is overlapped by the control gate 47 inside the contact hole 39.Further, each floating gate's bilateral edges overlap the adjacentburied regions 35.

FIGS. 4A-4D are diagrams illustrating a preferred embodiment of a methodfor fabricating a flash memory cell in accordance with the presentinvention and show sectional views taken along the line IV-IV' of FIG.3.

Referring to FIG. 4A, mask layer 33 is preferably formed by depositing asilicon oxide or a silicon nitride as thick as 3000 to 5000 Å on aP-type substrate 31 with the CVD method. The mask layer 33 is patternedwith photolithography to expose the substrate 31 in a stripe shape in afirst direction. Then, a buried region 35 is preferably formed byion-implanting an N-impurity such as phosphorus (p) or arsenic (As) byabout 10¹⁵ to 10¹⁶ /cm² dose with energy of about 30 to 50 KeV on theexposed portion of the substrate 30.

Referring now to FIG. 4B, the mask layer 33 is removed. Then, a fieldinsulating layer 37 is preferably formed by depositing a silicon oxideby 4000 to 6000 Å in thickness on the entire surface of the substrate31. Next, the field insulating layer 37 is patterned withphotolithography to expose the substrate 31 and thus form a plurality ofcontact holes 39 in a matrix form. The bilateral edges of the contacthole 39 overlap the adjacent buried regions 35. Then, a thermaloxidation is preferably performed on a part of the substrate 31 exposedby the contact hole 39 to form a gate oxide layer 41 200 to 400 Å inthickness.

As shown in FIG. 4C, a polysilicon doped with impurity is depositedpreferably using CVD on the field insulating layer 37 to fill thecontact hole 39 and an etch back is performed preferably usinganisotropic etching such as reactive ion etch to expose the fieldinsulating layer 37. At this time, the polysilicon remaining in thecontact hole 39 forms a floating gate 43 and thus the floating gate 43self-aligns with the contact hole 39. Both sides of the floating gate 43overlap the adjacent buried regions 35.

Referring to FIG. 4D, a thermal oxidation is performed on the surface ofthe floating gate 43 or a silicon oxide is deposited using CVD followedby a thermal oxidation to preferably form an interlevel insulating layer45, which is 300 to 500 Å in thickness. Then, preferably a polysilicondoped with impurity and a silicon oxide are sequentially deposited 3000to 4000 Å and 2000 to 4000 Å in respective thickness on the fieldinsulating layer 37 and the interlevel insulating layer 45 using CVD.Additionally, the silicon oxide and the polysilicon are sequentiallypatterned with photolithography to overlap the floating gate 43 in astriped shape in the second direction to form a control gate 47 and acap oxide layer 49, respectively.

In the preferred embodiment of a method of fabricating the flash memorycell according to the present invention, the field insulating layerhaving a plurality of contact holes in a matrix form on the substrate isformed based on the buried region having a striped shape in the firstdirection. Then, after paving the gate oxide layer and depositing thepolysilicon doped with impurity, the polysilicon is etched-back toremain only in the contact hole formed on the field insulating layer,which forms the floating gate and simultaneously separates a device.Therefore, the fabrication processes can be simplified and theintegration can be enhanced by self-aligning the floating gate in thecontact hole.

The foregoing embodiments are merely exemplary and are not to beconstrued as limiting the present invention. The present teaching can bereadily applied to other types of apparatuses. The description of thepresent invention is intended to be illustrative, and not to limit thescope of the claims. Many alternatives, modifications, and variationswill be apparent to those skilled in the art.

What is claimed is:
 1. A method of fabricating a flash memory cell,comprising the steps of:ion-implanting an impurity into a substrate toform buried regions extending in a first direction; depositing aninsulating layer on the substrate after ion-implanting the impurity;patterning the insulating layer to form a field insulating layer havinga plurality of contact holes arranged in a matrix, wherein the contactholes expose the substrate; forming gate insulating layers on theexposed portions of the substrate in the contact holes; forming afloating gate on each of the gate insulating layers such that thefloating gates an self-aligned in the contact holes; forming aninterlevel insulating layer on each of the floating gates; and formingcontrol gates extending in a second direction on the interlevelinsulating layers, wherein the second direction crosses the firstdirection on the interlevel insulating layers.
 2. The method offabricating a flash memory cell according to claim 1, wherein a densityof the flash memory cell is increased.
 3. The method of fabricating aflash memory cell according to claim 1 wherein a planarity of a flashmemory cell top surface is improved.
 4. The method of fabricating aflash memory cell according to claim 1, wherein the buried regions andthe control gates have striped shapes that are perpendicular.
 5. Themethod of fabricating a flash memory cell according to claim 1, furthercomprising depositing an insulating layer on the substrate to form amask layer before performing the ion-implanting step.
 6. The method offabricating a flash memory cell according to claim 5, wherein the fieldinsulating layer is approximately between 4000 and 6000 Å in thickness.7. The method of fabricating a flash memory cell according to claim 1,wherein lengthwise edges of adjacent buried regions are exposed in thestep of forming the contact holes.
 8. The method of fabricating a flashmemory cell according to claim 1, wherein the gate insulating layer isapproximately between 200 and 400 Å in thickness.
 9. The method offabricating a flash memory cell according to claim 1, wherein the stepof forming the floating gate comprises the steps of:depositing apolysilicon doped with impurity on the field insulating layer to fillthe contact holes; and etching-back the polysilicon to expose the fieldinsulating layer to form the floating gates in the contact holes. 10.The method of fabricating a flash memory cell according to claim 1,wherein the interlevel insulating layer is formed by treating a surfaceof the floating gates with thermal oxidation.
 11. The method offabricating a flash memory cell according to claim 1, wherein theinterlevel insulating layer is formed by depositing silicon oxide on thefloating gates.
 12. The method of fabricating a flash memory cellaccording to claim 1, wherein interlevel insulating layer isapproximately between 300 and 500 Å in thickness.
 13. The method offabricating a flash memory cell according to claim 1, further comprisingdepositing a silicon oxide on the control gates to form a cap oxidelayer.
 14. The method of claim 1, wherein the step of forming a floatinggate on each of the gate insulating layers comprises forming thefloating gates at a level above the buried regions.
 15. A method offabricating a flash memory cell, comprising the steps of:exposing asubstrate of a first conductivity type in a striped shape extendintg ina first direction; implanting an impurity of a second conductivity typeinto the exposed substrate to form buried regions; depositing aninsulating layer on the substrate after implanting the impurity, andpatterning the insulating layer to form a field insulating layer havinga plurality of contact holes, arranged in a matrix, that expose thesubstrate; forming a gate oxide layer by thermally oxidizing thesubstrate exposed in the contact holes; depositing a polysilicon dopedwith an impurity on the field insulating layer including the contacthole and etching-back the deposited polysilicon, to form a floating gateself-aligned in the contact holes; forming an interlevel insulatinglayer on the floating gates; and forming control gates extending in asecond direction on the interlevel insulating layer, wherein the seconddirection crosses the first direction.
 16. The method of claim 15,wherein a density of the flash memory cell is increased.
 17. The methodof claim 15, wherein the buried regions and the control gates havestriped shapes that are perpendicular.
 18. The method of claim 15,further comprising a step of depositing a silicon oxide on the controlgates to form a cap oxide layer.
 19. The method of claim 15, wherein thestep of depositing a polysilicon doped with an impurity on the fieldinsulating layer comprises depositing the polysilicon at a level abovethe buried regions so that floating gates, self-aligned in the contactholes, are formed at a level above the buried regions.
 20. A method offorming a flash memory cell, comprising the steps of:forming a pluralityof source and drain regions in a substrate; depositing an insulatinglayer on the substrate after forming the source and drain regions;patterning the insulating layer to create a plurality of contact holes,arranged in a matrix, that expose portions of the substrate betweenadjacent source and drain regions, wherein the patterned insulatinglayer also forms a field insulating layer that defines active regions ofthe substrate; forming gate oxide layers on the exposed portions of thesubstrate in the contact holes; forming floating gates that areself-aligned in the contact holes, and that are arranged at a levelabove the source and drain regions; forming an interlevel insulatinglayer on the floating gates; and forming control gates on the interlevelinsulating layer.
 21. The method of claim 20, wherein the patterningstep also exposes top surface portions of the substrate that arepositioned over edges of adjacent source and drain regions.